1. Field of the Invention
This disclosure relates to internal display port (iDP) interface test method and device, and more particularly to a method and a device for testing a sink device in an iDP interface.
2. Discussion of the Related Art
The applications for a liquid crystal display have increasingly widened due to its characteristics such as light weight, thin profile, and low power consumption driving. The liquid crystal display is used in a portable computer such as a notebook PC, an office automation device, an audio/video device, an indoor and outdoor advertisement display device, or the like. The liquid crystal display controls electric fields applied to liquid crystal cells so as to modulate light provided from a backlight unit, thereby displaying images.
In order to satisfy needs for high definition display performance from users, the liquid crystal display has increasingly implemented high image quality images at high channel transmission bandwidth and high frame refresh rate for video data. At present, in a television set system, video data transmission between a system on chip (“SoC”) generating video data to be displayed on a liquid crystal display panel and a timing controller controlling operation timings of driving circuits of the liquid crystal display panel uses an LVDS (Low Voltage Differential Signaling) interface. The LVDS interface is advantageous in that it has low power consumption and is less influenced by external noise due to use of low voltage swing level and differential signal pair, but is inappropriate for transmission of video data of high resolution due to the limitation of the data transmission rate.
A DP (Display Port) interface is an interface regulated by Video Electronics Standards Association (VESA) and is an interface scheme which integrates LVDS, which is the existing internal interface standard, with DVI (Digital Visual Interface) which is an external connection standard into one. The DP interface is a technique which cannot only make an internal connection between chips but also make an external connection between products by digital. Since two divided interfaces are integrated into one, and thus it is possible to support higher color depth and resolution by widening data bandwidth. The DP interface has the bandwidth of the maximum 10.8 Gbps which is twice or more that of the existing DVI (maximum 4.95 Gbps), and can simultaneously transmit six streams of the maximum 1080i (three 1080p) through one connection by supporting multi-streams using a micro-packet architecture. In addition, the DP interface mounts bidirectional auxiliary channels of 1 Mbps bandwidth and can thereby support applications such as a screen chatting and an internet telephone (VoIP) together.
FIG. 1 is a diagram illustrating a circuit configuration for a sink jitter tolerance test which is presented by the DP interface standard.
With reference to FIG. 1, the DP interface test device includes a stress signal generator (SSG) 51, a clock pattern generator 52, an auxiliary channel controller 53, and a test fixture 54.
A reception side DP sink device 55 is an element to be tested and is used as a reception circuit in the DP interface. The stress signal generator 51, the clock pattern generator 52, and the auxiliary channel controller 53 are connected to the lane input terminals and the auxiliary input terminals of the test fixture 54.
The test fixture 54 is connected to the reception side DP sink device (55) via a test connector, and is also connected to the stress signal generator 51, the clock pattern generator 52, and the auxiliary channel controller 53 via another test connector. The test fixture 54 relays signal transmission without frequency loss through the impedance matching of the loads connected to both of the connectors. The test fixture 54 includes an HPD (Hot Plug Detect) terminal in addition to the terminals connected to main link lanes and the auxiliary channel terminals. In the test method for the DP interface, the HPD lets a connection state between the test fixture 54 and the reception side DP sink device 55 known.
The stress signal generator 51 outputs test data including inter-symbol interference (ISI), random jitter (RJ), and sinusoidal jitter (SJ), and the like. The test data output from the stress signal generator 51 is a differential signal pair having positive and negative signals and is transmitted to the test fixture 54 via the main link lanes each of which is formed by a pair of signal lines.
The clock pattern generator 52 generates D24.3 (Quad-Rate Clock Pattern) clock signals which are defined in the DP interface standard, in order to reflect a crosstalk component which has influence on transmission lines. The D24.3 clock signal pattern is a clock pattern such as 11001100. The clock signals output from the clock pattern generator 52 are transmitted via both of the lanes in each of the main link lanes via which the test data is transmitted.
A tester sets one link rate of 1.62 Gbps and 2.70 Gbps which are transmission rates by setting LINK_BW_SET (address 0x100) of DPCD (Display Port Configuration Data) using the auxiliary channels each time a test is performed, and, in the same manner, sets lanes to be tested by setting LANE_COUNT_SET (address 0x101). Typically, the sink device stress test is classified into a link clock lock test, a symbol lock test, PRBS (Pseudo Random Bit Sequence) counter test, and a BER (Bit Error Rate) test.
In the link clock lock test, the stress signal generator 51 transmits test data where jitter is inserted into the D10.2 pattern defined in the DP interface standard. The reception side DP sink device 55 stores a recovery error amount which is generated when recovering the D10.2 pattern into which jitter is inserted, in a designated field of an internal DPCD register. The tester makes a request for the recovery error amount for the link clock lock test via the auxiliary channel controller 53, monitors the recovery error amount for the link clock lock test which is sent from the reception side DP sink device 55, and can thereby check how well the reception side DP sink device 55 recovers the test data.
In the symbol lock test, the stress signal generator 51 transmits a symbol lock pattern into which jitter is inserted, and the reception side DP sink device 55 stores a recovery error amount which is generated when recovering the symbol lock pattern into which jitter is inserted, in a designated field of the internal DPCD register. The tester makes a request for the recovery error amount for the symbol lock test via the auxiliary channel controller 53, monitors the recovery error amount for the symbol lock test which is sent from the reception side DP sink device 55, and can thereby check how well the reception side DP sink device 55 recovers the test data.
If link training via the main link lanes satisfies conditions for passing the link clock lock test and the symbol lock test, the stress signal generator 51 changes the test data pattern to a PRBS7 pattern which is transmitted after errors are inserted thereinto in an amount defined regarding the pattern. The reception side DP sink device 55 counts errors in the received PRBS7 pattern and stores a result thereof in a designated field of the internal DPCD register. The tester makes a request for the error count result via the auxiliary channel controller 53, monitors the error count result sent from the reception side DP sink device 55, and can thereby check whether or not the error counter of the reception side DP sink device 55 normally works.
As above, when all the functions of the reception side DP sink device 55 are verified, the stress signal generator 51 transmits the PRBS7 pattern into which jitter is inserted for a given time, and the reception side DP sink device 55 can pass the test if BER detected by the reception side DP sink device 55 is equal to or less than 1E-9 errors/sec for the given time.
The DP interface test method requires auxiliary channels AUX and also requires the DPCD register inside the reception side DP sink device 55. Further, the DP interface test method requires separate lanes for transmitting auxiliary channels in addition to the main link lanes for transmitting data, and requires the DPCD register and logics processing the register. In addition, the DP interface performs reading and writing through auxiliary channel communication and requires interface software for checking it. Therefore, costs for realizing the DP interface test method are high.
In recent years, VESA has defined an iDP interface standard. The iDP interface has been optimized as an interface between a System-on-chip (SoC) and a timing controller of a display device based on the existing DP interface. The iDP interface supports the serial data link rate of 3.24 Gbps for the lanes for transmitting the differential signal pair, and thus it is possible to transmit video data of high color depth, resolution, and frame refresh rate at a low lane count. The iDP interface does not use clock transmission lines separately in the same manner as the DP interface, and thereby it is necessary for a reception circuit Rx to perform a CDR (Clock and Data Recovery) process for recovering clock signals.
On the other hand, since there are no auxiliary channels AUX in the iDP interface, a reception side sink device cannot be tested in the same manner as the DP interface.